The field of the invention is integrated circuit fabrication, in particular fabrication on SOI wafers.
Shallow trench isolation (STI) has become standard in submicron integrated circuit processing, including silicon on insulator (SOI) processing, because of its size benefits.
A problem in small size devices, especially narrow devices (less than about 500 nm) is that of maintaining a stable threshold voltage.
The invention relates to an SOI integrated circuit employing shallow trench isolation, in which the walls of the transistor active area have a nitridized oxide layer grown on them, thereby preventing the diffusion of dopants out of the transistor body.